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Intel showcases future tech at IDF





Desktop processor roadmap

According to an Intel spokesperson, the Conroe system is about 35 percent faster than a P4EE system.
(click for larger image)
Conroe will be the keyword for Intel-based desktop systems launched in the later part of this year. Manufactured based on the power-efficient Intel Core microarchitecture, Conroe is a dual-core processor set to succeed the current Presler chip. According to Intel, Conroe is 40 percent faster than the Pentium D Processor 950, while offering 40 percent savings in power.

According to the roadmap given by Intel, a new 965 chipset will also be introduced in the second half of the year for the Conroe processor. At the same time, a new version of the Extreme Edition processor, that works on the current 975 chipset, will also be available.

Kentsfield, also based on the Intel Core microarchitecture, will be Intel's first quad-core processor for the top-of-the-line desktop PC market. It is expected to start shipping in the first quarter of 2007.

Tera-Scale Computing Research Program
This is one of the new initiatives announced by Intel at IDF where the chipmaker will collaborate with university researchers to develop computing platforms for the future. The program will cover key technologies in silicon, platform and software developments which can improve the operation and implementation of multi-core systems. The goal, within the next 10 years, is to deliver processors with tens and possibly hundreds of cores.

According to Intel's chief technology officer, Justin Rattner, who was speaking at the pre-IDF briefing, the challenge in multi-core systems is not putting the processors together. That's the easy part, he claims. Rather, it's the whole lot of architectural work required to take advantage of the multi-core platform. He pointed out common issues such as the interconnects between processors and the memory bandwidth as examples.

As a further example, Rattner talked about how Intel is working on Transactional Memory research to improve the way various cores in a processor access the same memory for data.

 

 

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